`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:16:53 04/05/2011 
// Design Name: 
// Module Name:    RegFile 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module RegFile(clk, readReg1, readReg2, writeReg, writeData, reset, RegWrite, readData1, readData2, mt);
    input clk;
    input [3:0] readReg1;
    input [3:0] readReg2;
    input [3:0] writeReg;
    input [15:0] writeData;
    input RegWrite;
	 input reset;
    output [15:0] readData1;
    output [15:0] readData2;
	 output [15:0] mt; //confused about managing this

	reg [15:0] readData1;
	reg [15:0] readData2;
	reg [15:0] mt;
	reg [15:0] register [0:15];
	
	always @ (posedge clk) //Write data
	begin
		if (RegWrite & ~(writeReg)) register[writeReg] <= writeData;
	end
	
	always @ (negedge clk) //Read data
	begin
		readData1 <= register[readReg1];
		readData2 <= register[readReg2];
		mt <= register[4'b0101];
	end
	
/*	always @ (posedge reset)
	begin
		register[4'd0] <= 0;
		register[4'd1] <= 0;
		register[4'd2] <= 0;
		register[4'd3] <= 0;
		register[4'd4] <= 0;
		register[4'd5] <= 0;
		register[4'd6] <= 0;
		register[4'd7] <= 0;
		register[4'd8] <= 0;
		register[4'd9] <= 0;
		register[4'd10] <= 0;
		register[4'd11] <= 0;
		register[4'd12] <= 0;
		register[4'd13] <= 0;
		register[4'd14] <= 0;
		register[4'd15] <= 0;
	end
*/
endmodule
